Open To Work
MURALI KRISHNA MINDI
Kuwait City,jaleeb,block 4,Kuwait
Summary
Motivated and enthusiastic engineering graduate with a strong foundation in engineering principles and a passion for solving complex technical challenges. Detail-oriented and dedicated to delivering high-quality work while working collaboratively in a team environment. Eager to contribute to cutting-edge projects and develop technical expertise in the field.
Overview
4
4
years of post-secondary education
5
5
years of professional experience
Work History
Junior Electrical Engineer
Electrical engineer
Vishkapatnam, Andhara oradesh
05.2021 - 12.2025
- Assisted in designing electrical circuits for various engineering projects.
- Collaborated with senior engineers on troubleshooting electrical systems and components.
- Worked in light house to check all the light house electrical related probleums.
- Conducted tests on electrical devices to ensure compliance with safety standards.
Education
B.Tech - ECE
Lendi Institute of Engineering And Technology in Elctronics
05.2016 - 01.2020
Intermediate -
NRI Junior Kalsala
10th -
Raman Vidya Vihar
Skills
- C
- C
- Resilience
- Accountability
- Team Player
- Flexibility
- Multitasking
- System troubleshooting
- Electrical safety compliance
- Battery management systems
- Critical thinking
- Microcontroller programming
- Electrical measurements
- Wireless communication
Civil Id
299060404655, 11/04/27
Languages
- Telugu
- Hindi
- English
- Telugu
- Hindi
Hobbies and Interests
- Playing outdoor sports
- Cricket
- Volleyball
- Badminton
- Swimming
Projects
EST PATTERN GENERATOR FOR PSEUDO EXHAUSTIVE TESTING USING LFSR, Pseudo Exhaustive testing with test pattern generator based upon VLSI Implementation of Linear Feedback Shift Register (LFSR). Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design Engineers to implement highly performing and testable digital systems. An 8-bit reconfigurable PRBSG LFSR design for logic BIST architecture is presented in the manuscript to generate pseudorandom test patterns, proposed Design ensures self-testing of the CUT by detecting random pattern testable faults. Flexibility is incorporated in the design by having multiple tap insertion points to XOR gates added at the inputs of flip-flops based on the number of primary outputs to be generated.
Achievements Awards
- Achieved first place and won the cup for university level inter-branch volleyball for three consecutive years during B.Tech.
- Winner in University level cricket championship for three years during B.Tech.
- Our project has been recognized as new innovation and journal is published in IJITEE.
Personal Information
- Passport Number: C2770654
- Date of Birth: 04/06/99
- Gender: Male
- Nationality: Indian
- Marital Status: Single
Languages
Hindi, English
First Language
Telugu
Proficient
C2
Timeline
Junior Electrical Engineer
Electrical engineer
05.2021 - 12.2025
B.Tech - ECE
Lendi Institute of Engineering And Technology in Elctronics
05.2016 - 01.2020
Intermediate -
NRI Junior Kalsala
10th -
Raman Vidya Vihar